A Discrete Geometry That Accidentally Produces Good Quantum Error Correction

By Raghu Kulkarni, SSMTheory Group, IDrive Inc.

While working on a discrete geometry model of spacetime-the Selection—Stitch Model—we found that the Face-Centered Cubic lattice produces an unusually high-rate quantum error correction code. The code is patent-pending (US Provisional 64/008,236), a paper has been submitted
(https://doi.org/10.5281/zenodo.19078942), and the architecture could be built on hardware that exists today.

Background

Our SSMTheory group has been developing a model where the vacuum has a discrete structure: a Face-Centered Cubic (FCC) lattice, the same geometry that describes atomic packing in metals like copper and aluminum. It is also the densest sphere packing in three dimensions (the Kepler conjecture, proved by Thomas Hales in 2005).

In this lattice, every node connects to exactly 12 neighbours (K = 12). The model uses this geometry to derive several cosmological observables from a small set of parameters.

During this work, we asked a side question: does this lattice have any use in quantum error correction?

The Code

Quantum computers use error correction codes that spread logical qubits across many physical qubits so that errors can be detected and fixed. The standard approach—Google’s surface code on a square lattice (K = 4)—requires roughly 1,000 physical qubits per logical qubit. Three-dimensional codes on a cubic lattice (K = 6) encode 3 logical qubits from 108 physical qubits: a 2.8% rate.

We placed qubits on the edges of the FCC lattice, defined stabilizer checks on the octahedral voids and vertices, and ran a 60-line Python verification.

At lattice size L=4, the code encodes 130 logical qubits in 192 physical qubits—a 67.7% encoding rate. At L=6: 434 logical qubits from 648 physical qubits. The formula is k = 2L3 + 2, converging to a 2/3 rate asymptotically.

The reason: the FCC lattice has 3L3 edges but only L3 − 2 independent stabilizer constraints. Two-thirds of the degrees of freedom are unconstrained and become logical qubits.

Figure 1: *
The FCC lattice (a) versus the cubic lattice (b). The FCC has 192 edge-qubits with 62 constraints, leaving 130 logical qubits. The cubic lattice has 108 edges and 105 constraints, leaving 3. Bottom row: octahedral stabilizer (d), tetrahedral logical qubit (e), ABC hexagonal layers (f).

Distance and Decoder

The minimum distance is d = 3, proven rigorously. We exhaustively checked all 18,336 weight-2 error patterns at L=4 and all 209,628 at L=6: none are undetectable. Weight-3 errors can slip through—34 Z-type and 12 X-type logical operators of weight 3 exist. The distance does not grow with lattice size.

We implemented a minimum-weight perfect matching (MWPM) decoder adapted to the K = 12 geometry. At physical error rate p = 0.001 (current best superconducting gate fidelities), the block logical error rate across all 130 qubits is 1.2%. Without the code, 130 bare qubits would fail 12.2% of the time—a coding gain of 10×. At p = 0.0005, decode success reaches 99.9% with a 63× coding gain.

The rate comparison with the cubic toric code is 24× higher, though at lower distance (d = 3 vs d = 4). This is not an apples-to-apples comparison; the FCC code trades distance for rate.

Figure 2: *
(a) Rate comparison. (b) Verified parameters with d = 3 proven. (c) Logical qubits growing with lattice size.
(d) Distance proof: exhaustive weight-≤ 2 elimination plus constructive weight-3 codewords. (e) Rate-distance tradeoff.

Limitations

A distance-3 code corrects one error per round. The block error rate scales as O(k · p), offering a constant suppression factor that does not improve with system size. This makes the FCC code a complement to surface codes, not a replacement: useful when you want many noisy logical qubits (variational algorithms, quantum simulation) rather than a few clean ones (deep fault-tolerant circuits).

The MWPM decoder finds globally optimal defect pairings but runs in O(n3) time. Faster approximate decoders (Union-Find, belief propagation) trade some accuracy for real-time speed.

Whether the distance can be pushed above 3 while retaining high rate—via tetrahedral void stabilizers, product constructions, or subspace restrictions—is an open question.

Who Could Build This

The code requires 12-way connectivity per qubit. That sounds like a 3D fabrication problem, but it isn’t.

The FCC lattice decomposes naturally into three hexagonal sheets stacked in the crystallographic ABC sequence. Each sheet is a flat 2D lattice with K = 6 in-plane connectivity—standard planar fabrication. The 12-way connectivity comes from stacking: each qubit connects to 6 neighbours on its own sheet, 3 on the sheet above, and 3 on the sheet below. K = 6 + 3 + 3 = 12.

This means you build three at chips using existing processes and bond them together with vertical connections (through-silicon vias, indium bumps, or optical links). No 3D crystal growth. No exotic fabrication. Three 2D sheets, stacked.

Superconducting platforms. IBM already bonds multiple chips together in their Heron architecture. QuantWare’s VIO routes connections vertically through stacked chiplets. Both would need to switch from square to hexagonal qubit layout and add the ABC offset alignment—a mask redesign, not a process change.

Neutral atom arrays. QuEra, Pasqal, and Atom Computing trap atoms in optical lattice planes. Three planes with FCC offset spacing, connected by inter-plane laser links, would implement the code directly. At 10,000 physical qubits, the FCC code would yield roughly 6,700 logical qubits.

Photonic networks. Programmable waveguide meshes can establish arbitrary connectivity between three planar photonic chips.

Interactive Visualization

An interactive 3D visualization of the FCC code is available at:

https://raghu91302.github.io/ssmtheory/ssm_qec_fcc.html

Figure 3: *
Interactive visualization: lattice structure, edge qubits, octahedral stabilizers, tetrahedral logical qubits, rate explanation, and error detection.

Status

The patent (US Provisional Application 64/008,236) was filed on March 17, 2026. A second provisional (64/008,866) covering the three-chip manufacturing method was filed on March 18, 2026. The paper has been submitted (preprint: https://doi.org/10.5281/zenodo.19078942). The complete verification code—including the exhaustive distance proof and MWPM decoder—is in the manuscript appendices.


Raghu Kulkarni leads the SSMTheory Group at IDrive Inc. in Calabasas, California. The physics papers and QEC results are available at https://idrive.com/ssmtheory.

IDrive is a cloud storage and computing company headquartered in Calabasas, CA.